Isolation region fabrication for replacement gate processing

ABSTRACT

A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.

CROSS-REFERENCE TO RELATED APPLICATION

This is an application for reissue of U.S. Pat. No. 8,643,109, and is acontinuation of application Ser. No. 15/015,546, which is also anapplication for reissue of U.S. Pat. No. 8,643,109, which application isa divisional of U.S. application Ser. No. 13/213,713, filed on Aug. 19,2011, which is herein incorporated by reference in its entirety.

BACKGROUND

This disclosure relates generally to the field of integrated circuit(IC) manufacturing, and more specifically to isolation regionfabrication for electrical isolation between semiconductor devices on anIC.

ICs are formed by connecting isolated active devices, which may includesemiconductor devices such as field effect transistors (FETs), throughspecific electrical connection paths to form logic or memory circuits.Therefore, electrical isolation between active devices is important inIC fabrication. Isolation of FETs from one another is usually providedby shallow trench isolation (STI) regions located between active siliconislands. An STI region may be formed by forming a trench in thesubstrate between the active devices by etching, and then filling thetrench with an insulating material, such as an oxide. After the STItrench is filled with the insulating material, the surface profile ofthe STI region may be planarized by, for example, chemical mechanicalpolishing (CMP).

However, use of raised (or regrown) source/drain structures, which maybe employed to achieve lower series resistances of the IC or to strainFET channels, may exhibit significant growth non-uniformities at theboundary between a gate and an STI region, or when the opening in whichthe source/drain structure is formed is of variable dimensions. Thisresults in increased variability in FET threshold voltage (V_(t)),delay, and leakage, which in turn degrades over-all product performanceand power. One solution to such boundary non-uniformity is to requireall STI regions to be bounded by isolation regions. However, inclusionof such isolation region structures may limit space available forwiring, device density, and increase the load capacitance, therebyincreasing switching power of the IC.

BRIEF SUMMARY

In one aspect, a semiconductor structure includes a silicon-on-insulator(SOI) substrate, the SOI substrate comprising a bottom silicon layer, aburied oxide (BOX) layer, and a top silicon layer; a plurality of activedevices formed on the top silicon layer; and an isolation region locatedbetween two of the active devices, wherein at least two of the pluralityof active devices are electrically isolated from each other by theisolation region, and wherein the isolation region extends through thetop silicon layer to the BOX layer.

Additional features are realized through the techniques of the presentexemplary embodiment. Other embodiments are described in detail hereinand are considered a part of what is claimed. For a better understandingof the features of the exemplary embodiment, refer to the descriptionand to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Referring now to the drawings wherein like elements are numbered alikein the several FIGURES:

FIG. 1 illustrates a flowchart of an embodiment of a method of isolationregion fabrication for replacement gate processing.

FIG. 2A is a cross sectional view illustrating an embodiment of asemiconductor structure including dummy gates on a silicon-on-insulator(SOI) substrate.

FIG. 2B is a top view illustrating an embodiment of the semiconductorstructure of FIG. 2A that comprises fins for formation of fin fieldeffect transistors (finFETs).

FIG. 3 is a cross sectional view illustrating the semiconductorstructure of FIG. 2A after formation of an interlevel dielectric layer(ILD) over the dummy gates.

FIG. 4 is a cross sectional view illustrating the semiconductorstructure of FIG. 3 after application and patterning of photoresist.

FIG. 5 is a cross sectional view illustrating the semiconductorstructure of FIG. 3 after removal of an exposed dummy gate to form anisolation region trench.

FIG. 6 is a cross sectional view illustrating the semiconductorstructure of FIG. 4 after removal filling the isolation region trenchwith an isolation dielectric.

FIG. 7 is a cross sectional view illustrating the semiconductorstructure of FIG. 5 after formation of a hardmask layer over theisolation region trench.

FIG. 8 is a cross sectional view illustrating the semiconductorstructure of FIG. 6 after replacement gate processing.

DETAILED DESCRIPTION

Embodiments of a method for isolation region fabrication for replacementgate processing, and an IC including isolation regions, are provided,with exemplary embodiments being discussed below in detail. Instead ofplacing isolation regions at STI region boundaries, isolation regionsmay replace STI regions, as is described in U.S. patent application Ser.No. 12/951,575 (Anderson et al.), filed Nov. 22, 2010, which is hereinincorporated by reference in its entirety. A relatively dense,low-capacitance IC may be formed by replacement gate (i.e., gate-last)processing through use of a block mask that selectively allows removalof active silicon in a gate opening to form an isolation region. Theactive silicon is removed in a manner that is self-aligned to the dummygate, such that there is no overlap of gate to active area and henceminimal capacitance penalty.

FIG. 1 shows a flowchart of an embodiment of a method 100 of isolationregion fabrication for replacement gate processing. FIG. 1 is discussedwith reference to FIGS. 2-7. First, in block 101 of FIG. 1, asemiconductor structure including dummy gates, source/drain regions,spacers, is formed on a substrate using regular semiconductor processingtechniques, and an interlevel dielectric layer (ILD) is formed over thedummy gates. The semiconductor structure may also include raisedsource/drain regions located on either side of the dummy gatesunderneath the spacers is in some embodiments. The semiconductorstructure may include any appropriate semiconductor structure thatincludes dummy gates, including but not limited to a fin field effecttransistor (finFET) structure. An embodiment of such a semiconductorstructure 200A is shown in FIG. 2A. The substrate is asilicon-on-insulator substrate, including bottom silicon layer 201,buried oxide (BOX) layer 202, and top silicon layer 203. Dummy gates 204are located on top silicon layer 203. In some embodiments, a gatedielectric layer 207 is formed underneath each dummy gate 204. The dummygate structure 204 may be polysilicon in some embodiments. The gatedielectric layer 207 may be any appropriate dielectric material, and insome embodiments may include a bottom dielectric layer and a top metallayer. Spacers 205 are formed on either side of the dummy gates 204.FIG. 2B shows a top view of an embodiment of the semiconductor structure200A of FIG. 2A in which the top silicon layer 203 has been patterned toform fins for finFETs. In the semiconductor structure 200B of FIG. 2B,the dummy gates 204 wrap around and cover the fins that comprise topsilicon layer 203. After formation of the dummy gates 204, as shown inFIG. 3, ILD 301 is formed over the dummy gates 204 and spacers 205, andILD 301 is planarized such that the top surfaces of dummy gates 204 areexposed.

Returning to method 100, in block 102, a block mask is applied to thetop surface of the dummy gates and the ILD, and the block mask ispatterned to selectively expose the dummy gates that are to becomeisolation regions. The block mask may comprise, for example,photoresist. FIG. 4 shows an embodiment of the semiconductor structure200A after application and patterning of photoresist 401 to form theblock mask, which exposes a dummy gate 402. Then, turning again tomethod 100, in block 103, the exposed dummy gate is removed, and theportion of the top silicon layer located underneath the removed dummygate is etched down to the BOX layer to form an isolation region recess.FIG. 5 shows an embodiment of a device including an isolation regionrecess 501. The etch used to remove exposed dummy gate 402 and itsrespective gate dielectric layer 207, and to form the recess 501 in topsilicon layer 203, may be a sequential multistage etch. The sequentialmultistage etch may have 3 or 4 different stages depending on thematerials that make up dummy gate 204 and gate dielectric layer 207. Inembodiments in which the dummy gate 402 is polysilicon, dummy gate 402may be removed using a dry etch such as a bromine-based etch. Therespective gate dielectric layer 207 may next be removed using a wetetch, such as a hydrofluoric etch for example. In embodiments in whichrespective gate dielectric layer 207 includes a bottom dielectric layerand a top metal layer, the etch to remove the gate dielectric layer 207may be a 2-stage etch. Then, the recess 501 may be formed in the topsilicon layer 203 using a dry etch such as a bromine-based etch to etchdown to BOX layer 202.

Next, in method 100 of FIG. 1, in block 104, the recess that was formedduring the etch performed in block 103 is filled with an insulatingmaterial to form the isolation region, and the top surface of theinsulating material is planarized such as is shown in FIG. 6. In FIG. 6,the recess 501 is filled with an insulator, and the top surface of theinsulator is planarized, to form isolation region 601. The insulatorthat comprises isolation region 601 may include silicon dioxide orsilicon nitride in various embodiments. Then, flow of method 100proceeds to block 105, in which a hardmask layer is formed over theisolation region and the photoresist is removed. FIG. 7 shows anembodiment of a hardmask layer 701 formed over the isolation region 601.The hardmask layer 701 may be silicon nitride. The photoresist 401 isalso removed to expose the top surfaces of the remaining dummy gates204.

Lastly, in block 106 of method 100 of FIG. 1, replacement gateprocessing is performed on the remaining dummy gates, resulting in an ICdevice including electrical devices separated by isolation regions. Anexample of an IC device 800 including an isolation region 601 betweentwo active devices is shown in FIG. 7 8. Dummy gates 204 have beenreplaced with gate stacks 801 to form active FETs 802, including gatestacks 801, gate dielectric layer 207, spacers 205, and source/drain andchannel regions located underneath the devices in the top silicon layer203. The active FETs 802 may include raised source/drain regions (notshown) located under the spacers 205 in some embodiments. The activeFETs 802 are separated by the isolation region 601, which extends downto BOX layer 202, preventing electrical leakage between active FETs 802.The hardmask layer 701 acts to protect the isolation region 601 duringthe replacement gate processing. The hardmask layer 701 may be left onthe device 800 in some embodiments, or in other embodiments the hardmasklayer 701 may be removed after replacement gate processing is completed.FIGS. 2A-8 are shown for illustrative purposes only; a device formedusing method 100 may include any appropriate number, type, and layout ofFETs separated by any appropriate number and layout of isolationregions. For example, in some embodiments, two active devices in asemiconductor structure may have two isolation regions located betweenthe two active devices. Also, in some embodiments, the gate dielectriclayer that is initially formed underneath the dummy gate may be replacedduring the replacement gate processing. The finished active devices maycomprise finFETs in some embodiments, or any other appropriate type ofactive device that may be formed by replacement gate processing in otherembodiments.

The technical effects and benefits of exemplary embodiments includeformation of an IC having relatively high device density and lowcapacitance through replacement gate processing.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an”, and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

The invention claimed is:
 1. A semiconductor structure, comprising: asilicon-on-insulator (SOI) substrate, the SOI substrate comprising abottom silicon layer, a buried oxide (BOX) layer, and a top siliconlayer; a plurality of active devices formed on the top silicon layer;and an isolation region located between two of the plurality of activedevices, wherein at least two of the plurality of active devices areelectrically isolated from each other by the isolation region, whereinthe isolation region extends through the top silicon layer to the BOXlayer, wherein the isolation region further extends between a pair ofspacers that are located on the top silicon layer on either side of theisolation region, and wherein the isolation region further extendsthrough an interlevel dielectric (ILD) layer that is located over thepair of spacers.
 2. The semiconductor structure of claim 1, furthercomprising a hardmask layer located over the isolation region.
 3. Thesemiconductor structure of claim 2, wherein the hardmask layer comprisessilicon nitride.
 4. A semiconductor device comprising: a substrateincluding a top silicon layer that includes a fin; a first gatestructure disposed on the fin; a second gate structure disposed on thefin; an isolation region disposed between the first gate structure andthe second gate structure; a first spacer disposed on a first side ofthe isolation region and disposed on the top silicon layer; a secondspacer disposed on a second side of the isolation region and disposed onthe top silicon layer; and an interlevel dielectric (ILD) layer disposedon the first spacer and the second spacer, wherein the isolation regionextends between the first spacer and the second spacer, and wherein theisolation region extends through the ILD layer that is disposed on thefirst spacer and the second spacer.
 5. The semiconductor device of claim4, wherein the isolation region includes silicon nitride.
 6. Thesemiconductor device of claim 4, wherein the isolation region isdisposed below a silicon nitride layer.
 7. The semiconductor device ofclaim 4, wherein the isolation region electrically isolates the firstgate structure from the second gate structure.
 8. The semiconductordevice of claim 4, further comprising source/drain regions disposed onthe substrate, disposed on sides of the first and second gatestructures, and disposed below the first and second spacers.
 9. Thesemiconductor device of claim 4, wherein the substrate is asilicon-on-insulator substrate.
 10. The semiconductor device of claim 4,wherein a top surface of the isolation region is planarized.
 11. Thesemiconductor device of claim 4, further comprising channels disposedbelow the first gate structure and the second gate structure.
 12. Thesemiconductor device of claim 4, wherein the isolation region extendsthrough the ILD layer in a direction that is substantially parallel withrespect to a top surface of the substrate.
 13. The semiconductor deviceof claim 4, wherein the isolation region extends through the ILD layerin a direction that is substantially perpendicular with respect to a topsurface of the substrate.
 14. The semiconductor device of claim 4,wherein the ILD layer is disposed on a sidewall of the first spacer andon a sidewall of the second spacer.
 15. The semiconductor device ofclaim 4, wherein the ILD layer is disposed on a top surface of the firstspacer and on a top surface of the second spacer.
 16. The semiconductordevice of claim 4, wherein the isolation region contacts the ILD layer.